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a426316b series preliminary 64k x 16 cmos dynamic ram with edo page mode preliminary ( november , 2000, version 0.0) amic technology, inc. document title 64k x 16 cmos dynamic ram with edo page mode revision history rev. no. history issue date remark 0.0 initial issue november 15, 2000 preliminary
a426316b series preliminary 64k x 16 cmos dynamic ram with edo page mode preliminary ( november , 2000, version 0 .0) 1 amic technology, inc. features n organization: 65,536 words x 16 bits n part identification: - a426316b - a426316b - l (with self - refr esh mode) n high speed - 30/35/40 ns ras access time - 16/18/20 ns column address access time - 10/11/12 ns cas access time n low power consumption - operating: 75ma ( - 30 max) - standby: 3 ma (ttl) n separate cas ( ucas , lcas ) for byte selection n self refresh mode n 256 refresh cycles, 4 ms refresh interval n read - modify - write, ras - only, cas - before - ras , hidden refresh capability n ttl - compatible, three - state i/o n jedec standard packages - 400mil, 40 - pin soj - 400mil, 40/44 tsop type ii package n single 5v power supply/built - in vbb generator pin configuration pin descriptions n n soj n n tsop vcc i/o 0 i/o 1 nc a1 a2 a3 vcc a4 a5 a6 a7 nc i/o 13 i/o 14 i/o 15 vss a426316bs 21 we ras i/o 12 oe i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 0 nc nc vcc vss ucas lcas nc i/o 8 i/o 9 i/o 10 i/o 11 vss 20 19 18 12 16 17 13 14 15 11 10 9 8 7 6 5 4 3 2 1 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 vcc i/o 0 i/o 1 nc a1 a2 a3 a4 a5 a6 a7 nc i/o 13 i/o 14 i/o 15 vss a426316bv 23 we ras i/o 12 oe i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 0 nc nc vcc vss ucas lcas nc i/o 8 i/o 9 i/o 10 i/o 11 vss 22 21 20 14 18 19 15 16 17 13 10 9 8 7 6 5 4 3 2 1 24 25 26 27 28 29 30 31 32 35 36 37 38 39 40 41 42 43 44 vcc symbol description a0 ? a7 address inputs i/o 0 - i/o 15 data input/output ras row address strobe ucas column address strobe/upper byte control lcas column address strobe/low er byte control we write enable oe output enable vcc +5v power supply vss ground nc no connection
a426316b series prelimina ry ( november , 2000, version 0.0) 2 amic technology, inc. selection guide symbol description - 30 - 35 - 40 unit t rac maximum ras access time 30 35 40 ns t aa maximum column address access time 16 18 20 ns t cac maximum cas access time 10 11 12 ns t oea maximum output enable ( oe ) access time 10 11 12 ns t rc minimum read or write cycle time 65 70 75 ns t pc mi nimum edo page mode cycle time 12 14 15 ns i cc1 maximum operating current 95 85 75 ma i cc6 maximum cmos standby current 2 2 2 ma functional description the a426316b is a high performance cmos dynamic random access memory organized as 65,536 words x 1 6 bits. the a426316b is fabricated with advanced cmos technology and designed with innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. the a426316b features a high speed page mode operation in which high speed read, write and read - write are performed on any of the bits defined by the column address. the asynchronous column address uses an extremely short row address capture time to ease the system level timing constraints asso ciated with multiplexed addressing. output is tri - stated by a column address strobe ( ucas and lcas ) which acts as an output enable independent of ras . very edo ucas and lcas to output access time eases system design. all inputs are ttl compatible. edo page mode operation allows random access up to 256 x 16 bits within a page, with cycle time as short as 12/14/15 ns. the a426316b is best suited for graphics, di gital signal processing and high performance peripherals. the a426316b is available in jedec standard 40 - pin plastic soj package and 40/44 tsop type ii package.
a426316b series prelimina ry ( november , 2000, version 0.0) 3 amic technology, inc. block diagram ras clock generator upper byte data i/o buffer sense amp column decoder refresh controller address buffers we clock generator ucas clock generator substrate bias generator 256 x 256 x 16 array row decoder ras ucas a0 a7 a6 a5 a4 a3 a2 a1 vss vcc i/o 8 i/o 9 i/o 10 i/o 11 y0 - y7 256 x0 - x7 i/o 12 i/o 13 i/o 14 i/o 15 oe clock generator we oe lcas clock generator lcas 256 x 16 lower byte data i/o buffer i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 recommended operating conditions (ta = 0 c to +70 c) symbol description min. typ. max. unit vcc supply voltage 4.5 5.0 5.5 v vss 0.0 0.0 0.0 v v ih input voltage 2.4 - vcc + 1 v v il - 1.0 - 0.8 v
a426316b series prelimina ry ( november , 2000, version 0.0) 4 amic technology, inc. truth table function ras ucas lcas we oe address i/os notes standby h h h x x x high - z read: word l l l h l row/col. data out read: lower byte l h l h l row/col. i/o 0 - 7 = data out i/o 8 - 15 = high - z read: upper byte l l h h l row/col. i/o 0 - 7 = h igh - z i/o 8 - 15 = data out write: word(early) l l l l x row/col. data in write: lower byte(early) l h l l x row/col. i/o 0 - 7 = data in i/o 8 - 15 = x write: upper byte(early) l l h l x row/col. i/o 0 - 7 = x i/o 8 - 15 = data in read - write l l l h ? l l ? h row/co l. data out ? data in 1.2 edo - page - mode read: hi - z - first cycle - subsequent cycles l l h ? l h ? l h ? l h ? l h h h ? l h ? l row/col. col. data out data out 2 2 edo - page - mode write(early) - first cycle - subsequent cycles l l h ? l h ? l h ? l h ? l l l x x row/col. col. data in data in 1 1 edo - page - mode read - write - first cycle - subsequent cycles l l h ? l h ? l h ? l h ? l h ? l h ? l l ? h l ? h row/col. col. data in data in 1, 2 1, 2 hidden refresh read l ? h ? l l l h l row/col. data out 2 hidden refresh write l ? h ? l l l l x row/col. data in ? high - z 1 ras - only refresh l h h x x row high - z cbr refresh h ? l l l x x x high - z 3 self refresh (l - ver only) h ? l l l x x x high - z note: 1. byte write ma y be executed with either ucas or lcas active. 2. byte read may be executed with either ucas or lcas active. 3. only one cas signal ( ucas or lcas ) must be active.
a426316b series preliminary ( november , 2000, version 0.0) 5 amic technology, inc. absolute maximum ratings* input voltage (vin) . . . . . . . . . . . . . . . . . . . - 1.0v to +7.0v output voltage (vout) . . . . . . . . . . . . . . . . - 1.0v to +7.0v power supply voltage (vcc) . . . . . . . . . . - 1.0v to +7.0v operating temperature (t opr ) . . . . . . . . . . 0 c to +70 c storage temperature (t stg ) . . . . . . . . . - 55 c to +150 c soldering temperature x time (t sloder ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 c x 10sec power dissipation (p d ) . . . . . . . . . . . . . . . . . . . . . . . . 1w short circuit output current (iout) . . . . . . . . . . . . . 50ma latch - up current . . . . . . . . . . . . . . . . . . . . . . . . . . 200ma *comments stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the oper ational sections of these specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics (vcc = 5v 10%, vss = 0v, ta = 0 c to +70 c) symb ol parameter - 30 - 35 - 40 unit test conditions notes min. max. min. max. min. max. i il input leakage current - 10 +10 - 10 +10 - 10 +10 m a 0v vin +5.5v pins not under test = 0v i ol output leakage current - 10 +10 - 10 +10 - 10 +10 m a dout disabled, 0v vout +5.5v i cc1 operating current - 95 - 85 - 75 ma ras , ucas , lcas addr ess cycling t rc = min. 1, 2 i cc2 ttl standby power supply current - 3 - 3 - 3 ma ras = cas 3 v ih all other inputs 3 vss i cc3 refresh current ( ras only refresh) - 95 - 85 - 75 ma ras cycling, ucas = lcas = v ih , t rc = min. 1 i cc4 edo page mode current - 95 - 85 - 75 ma ras = v il , ucas , lcas address cycling t pc = min. 1, 2 i cc5 refre sh current ( cas - before - ras refresh ) - 95 - 85 - 75 ma ras , ucas , lcas cycling t rc = min. 1 i cc6 cmos standby power supply current - 2 - 2 - 2 m a ras = cas 3 vcc - 0.2v all other inputs 3 vss i cc7 self refresh mode current - 3 - 3 - 3 ma ras = cas vss + 0.2v all other inputs 3 vss v oh output high voltage 2.4 - 2.4 - 2.4 - v i out = - 5.0ma v ol output low voltage - 0.4 - 0.4 - 0.4 v i out = 4.2ma
a426316b series preliminary ( november , 2000, version 0.0) 6 amic technology, inc. ac characteristics (vcc = 5v 10%, vss = 0v, ta = 0 c to +70 c) # std symbol parameter - 30 - 35 - 40 unit notes min. max. min. max. min. max. 1 t rc random read or write cycle time 65 - 70 - 75 - ns 2 t rp ras precharge time 25 - 25 - 25 - ns 3 t ras ras pulse width 30 75k 35 75k 40 75k ns 4 t cas cas pulse width 5 - 6 - 7 - ns 5 t rcd ras to cas delay time 15 20 16 24 17 28 ns 6 6 t rad ras to column address delay time 10 14 11 17 12 20 ns 7 7 t rsh cas to ras hold time 10 - 10 - 10 - ns 8 t csh cas hold time 30 - 35 - 40 - ns 9 t crp cas to ras precharge time 5 - 5 - 5 - ns 10 t asr row address setup time 0 - 0 - 0 - ns 11 t rah row address hold time 5 - 6 - 7 - ns t t transition tim e (rise and fall) 2 50 2 50 2 52 ns 4, 5 t ref refresh period - 4 - 4 - 4 ms 3 12 t clz cas to output in low z 0 - 0 - 0 - ns 8 13 t rac access time from ras - 30 - 35 - 40 ns 6,7 14 t cac access time from cas - 10 - 11 - 12 ns 6, 13 15 t aa access time from column address - 16 - 18 - 20 ns 7, 13 16 t ar column address hold time from ras 26 - 28 - 30 - ns 17 t rcs read command setup time 0 - 0 - 0 - ns
a426316b series prelimina ry ( november , 2000, version 0.0) 7 amic technology, inc. ac characteristics (continued) (vcc = 5v 10%, vss = 0v, ta = 0 c to +70 c) # std symbol parameter - 30 - 35 - 40 unit notes min. max. min. max. min. max. 18 t rch read command hold time 0 - 0 - 0 - ns 9 19 t rrh read command hold time reference to ras 0 - 0 - 0 - ns 9 20 t ral column address to ras lead time 16 - 18 - 20 - ns 21 t coh output hold after cas low 5 - 5 - 5 - ns 22 t ods output disable setup time 0 - 0 - 0 - ns 23 t off output buffer turn - off delay time 0 6 0 6 0 6 ns 8, 10 24 t asc column address setup time 0 - 0 - 0 - ns 25 t cah column address hold time 5 - 5 - 5 - ns 26 t rps ras precharge setup time 50 - 60 - 70 - ns 27 t wcs write command setup time 0 - 0 - 0 - ns 11 28 t wch write command hold time 5 - 5 - 5 - ns 11 29 t wcr write command hold time to ras 26 - 28 - 30 - ns 30 t wp write command pulse width 5 - 5 - 5 - ns 31 t rwl write command to ras lead time 10 - 11 - 12 - ns 32 t cwl write command to cas lead time 10 - 11 - 12 - ns 33 t ds data - in setup time 0 - 0 - 0 - ns 12 34 t dh data - in hold time 5 - 5 - 5 - ns 12 35 t dhr data - in hold time to ras 26 - 28 - 30 - ns 36 t rmw read - modify - write cycle time 100 - 105 - 100 - ns 37 t rwd ras to we delay time (read - modify - write) 50 - 54 - 58 - ns 11
a426316b series prelimina ry ( november , 2000, version 0.0) 8 amic technology, inc. ac characteristics (continued) (vcc = 5v 10%, vss = 0v, ta = 0 c to +70 c) # std symbol parameter - 30 - 35 - 40 unit notes min. max. min. max. min. max. 38 t cwd cas to we delay time (read - modify - write) 26 - 28 - 30 - ns 11 39 t awd column address to we delay time (read - modify - write) 32 - 35 - 35 - ns 11 40 t rass ras pulse width (self refresh mode) 300 - 300 - 300 - m s 41 t cpn cas precharge time ( cas before ras ) 10 100k 10 100k 10 100k ns 42 t pc read or write cycle time (edo page) 12 - 14 - 15 - ns 14 43 t cpa access time from cas precharge (edo page) - 19 - 21 - 23 ns 13 44 t cp cas precharge time (edo page) 3 - 4 - 5 - ns 45 t prm edo page mode rmw cycle time 56 - 58 - 60 - ns 46 t crw edo page mode cas pulse width (rmw) - 44 - 46 - 48 ns 47 t rasp ras pulse width (edo page) 30 75k 3 5 75k 40 75k ns 48 t csr cas setup time ( cas - before - ras ) 0 - 0 - 0 - ns 3 49 t chr cas hold time ( cas - before - ras ) 7 - 8 - 8 - ns 3 50 t rpc ras to cas precharge time ( cas - before - ras ) 0 - 0 - 0 - ns 51 t roh ras hold time reference to oe 6 - 7 - 8 - ns 52 t oea oe access time - 10 - 11 - 12 ns 53 t oed oe to data delay 5 - 5 - 5 - ns 54 t oez output buffer turn - off delay from oe 0 5 0 6 0 6 ns 8
a426316b series prelimina ry ( november , 2000, version 0.0) 9 amic technology, inc. ac characteristics (continued) (vcc = 5v 10%, vss = 0v, ta = 0 c to +70 c) # std symbol parameter - 30 - 35 - 40 unit notes min. max. min. max. min. max. 55 t oeh oe command hold time 10 - 10 - 10 - ns 56 t cpt cas precharge time ( cas - before - ras counter test) 20 - 20 - 20 - ns notes: 1. i cc1 , i cc3 , i cc4 , and i cc5 depend on cycle rate. 2. i cc1 and i cc4 depend on output loading. specified values are obtained with the outputs open. 3. an ini tial pause of 200 m s is required after power - up followed by any 8 ras cycles before proper device operation is achieved. in the case of an internal refresh counter, a minimum of 8 cas - before - ras initialization cyc les instead of 8 ras cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than 8ms). 4. ac characteristics assume t t = 3ns. all ac parameters are measured with a load equival ent to one ttl loads and 50pf, v il (min.) 3 gnd and v ih (max.) vcc. 5. v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il . 6. operation within the t rcd (max.) limit in sures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then access time is controlled exclusively by t cac . 7. operation within the t rad (max.) limit insures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then access time is controlled exclusively by t aa . 8. assumes three state test load (5pf and a 380 w thevenin equivalent). 9. either t rch or t rrh must be satisfied for a read cycle. 10. t off (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. 11. t wcs , t wch , t rwd , t cwd and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.) and t wch 3 t wch (min.), the cycle is an early write cycle and data - out pins will remain open circuit, high impedance, throughout the entire cycle. if t rwd 3 t rwd (min.) , t cwd 3 t cwd (min.) and t awd 3 t awd (min.), the cycle is a read - modify - write cycle and the data out will contain data read from the selected cell. if neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. 12. these parameters are referenced to ucas and lcas leading edge in early write cycles and to we leading edge in read - modify - write cycle s. 13. access time is determined by the longer of t aa or t cac or t cpa . 14. t asc 3 t cp to achieve t pc (min.) and t cpa (max.) values. 15. these parameters are sampled and not 100% tested.
a426316b series prelimina ry ( november , 2000, version 0.0) 10 amic technology, inc. t ras(3) t rp(2) t rc(1) t crp(9) t csh(8) t rcd(5) t rsh(7) t cas(4) t asr(10) t crp(9) t rah(11) t asc(24) t cah(25) t rad(6) t ral(20) t rch(18) t rrh(19) t ar(16) t rcs(17) t roh(51) t oea(52) t rac(13) t aa(15) t cac(14) t clz(12) t oez(54) t off(23) high-z : high or low valid data-out row address column address i/o 0 ~ i/o 15 oe we a0 ~ a7 ucas lcas ras word read cycle
a426316b series prelimina ry ( november , 2000, version 0.0) 11 amic technology, inc. word write cycle (early write) t ras(3) t rp(2) t rc(1) t crp(9) t csh(8) t rcd(5) t rsh(7) t cas(4) t asr(10) t crp(9) t rah(11) t asc(24) t cah(25) t rad(6) t ral(20) t wch(28) : high or low row address column address i/o 0 ~ i/o 15 oe a0 ~ a7 ucas lcas ras t ar(16) t cwl(32) t rwl(31) t wp(30) t wcs(27) valid data-in t ds(33) t dh(34) we t wcr(29) t dhr(35)
a426316b series prelimina ry ( november , 2000, version 0.0) 12 amic technology, inc. word write cycle ( la te write) t ras(3) t rp(2 ) t rc(1) t crp(9) t csh(8) t rcd(5) t rsh(7) t cas(4) t asr(10) t crp(9) t asc(24) t cah(25) t rad(6) t ral(20) row address column address a0 ~ a7 ucas lcas ras t ar(16 ) t cwl(32) t rwl(31) t wp(30) t rah(11) t oeh(55) t oed(54) t ds(33) t dh(34) i/o 0 ~ i/o 15 : high or low oe we high-z vaild data-in t wcr(29) t dhr(35)
a426316b series prelimina ry ( november , 2000, version 0.0) 13 amic technology, inc. word read - modify - write cycle t ras(3) t rp(2) t rwc(36) t crp(9) t csh(8) t rcd(5) t rsh(7) t cas(4) t asr(10) t crp(9) t rah(11) t cah(25) t rad(6) row address column address a0 ~ a7 ras t ar(16) t rwl(31) t asc(24) t cwl(32) t awd(39) t cwd38) t rwd(37) t wp(30) t oea(52) t oez(54) t clz(12) t cac(14) t oed(53) t aa(15) t rac(13) t ds(33) t dh(34) high-z data-out data-in : high or low i/o 0 ~ i/o 15 oe ucas t oeh(55) t rcs(17) lcas we
a426316b series prelimina ry ( november , 2000, version 0.0) 14 amic technology, inc. edo page mode word read cycle t rasp(47) t rp(2) ras t cas(4) t cas(4) t cas(4) t rcd(5) t csh(8) t crp(9) t crp(9) t pc(42) t rsh(7) t asr(10) t rah(11) t rad(6) t ar(16) t ral(20) a0 ~ a7 oe ucas i/o 0 ~ i/o 15 : high or low t asc(24) t cp(44) t csh(8) t asc(24) t cah(25) t cah(25) row column column column t rch(25) t rcs(17) t rcs(17) t rch(25) t rcs(17) t cah(25) t rrh(19) t off(23) t oez(54) t aa(15) t oea(52) t oep(41) t cac(14) t clz(12) t oez(54) t cpa(43) t oes(26) t aa(15) t oea(52) t coh (21) t cac(14 ) t rac(13) t cac(14) t clz(12) data-out data-out data-out lcas we
a426316b series prelimina ry ( november , 2000, version 0.0) 15 amic technology, inc. edo page mode early word write cycle t rasp(47) t rp(2) ras ucas lcas t cas(4) t cp(44) t cas(4) t cp(44) t cas(4) t rcd(5) t csh(8) t crp(9) t crp(9) t pc(42) t rsh(7) t asr(10) t rah(11) t rad(6) t asc(24) t cah(25) t asc(24) t cah(25) t cah(25) t asc(24) t ral(20) row column column a0 ~ a7 we t cwl(32) t wch(28) t wcs(27) t wcs(27) column t cwl(32) t wch(28) t wcs(27) t wch(28) t cwl(32) t rwl(31) t wp(30) t wp(30) t wp(30) t dh(34) t ds(33) t dh(34) t ds(33) t ds(33) t dh(34) data-in data-in data-in i/o 0 ~ i/o 15 oe : high or low
a426316b series prelimina ry ( november , 2000, version 0.0) 16 amic technology, inc. edo page mode word read - modify - write cycle t rasp(47) ras t cas(4) t cp(44) t cas(4) t cp(44) t cas(4) t rcd(5) t csh(8) t crp(9) t crp(9) t pcm(45) t rsh(7) t rp(2) t asr(10) t rah(11) t rad(6) t asc(24) t cah(25) t asc(24) t cah(25) t asc(24) t cah(25) t ral(20) t rcs(17) t cwd(38) t rwd(37) t cwl(32) t cwd(38) t cwl(32) t cwd(38) t cwl(32) t rwl(31) t oea(52) t oea(52) t oea(52) t wp(30) t wp(30) t wp(30) t awd(39) t awd(39) t awd(39) t roh(51) t cac(14) t aa(15) t rac(13) t oed(53) t oez(54) t ds(33) t aa(15) t cpa(43) t dh(34) t oez(54) t oed(53) t ds(33) t dh(34) t oez(54) t ds(33) t oed(53) t dh(34) t aa(15) t cpa(43) t clz(12) t clz(12) t clz(12) high-z : high or low i/o 0 ~ i/o 15 oe ucas a0 ~ a7 data-out data-in data-out data-in data-out data-in row column column column t oeh(55) lcas we
a426316b series prelimina ry ( november , 2000, version 0.0) 17 amic technology, inc. ras only refresh cycle cas before ras refresh cycle t ras(3) t rp(2) t rc(1) ras t crp(9) t rpc(50) t asr(10) t rah(11) a0 ~ a7 ucas lcas : high or low row note: we, oe = don't care. t ras(3) t rp(2) t rc(1) ras t rp(2) t rpc(50) t cpn(41) t csr(48) t chr(49) t off(23) i/o 0 ~ i/o 15 ucas lcas high-z : high or low note: we, oe, a0 ~ a7 = don't care.
a426316b series prelimina ry ( november , 2000, version 0.0) 18 amic technology, inc. timing waveform of cas - before - ras refresh counter test cycle t cac (14) t ras (3) t rsh (7) t rp (2) t cpt (56) t chr (49) t cas (4) t ral (20) t cah (25) t aa (15) t cac (14) t clz (12) t off (23) t rch (18) t rcs (17) t rrh (19) t rwl (31) t cwl (32) t wp (30) t wch (28) t wcs (27) t dh (34) t ds (33) t wp (30) t cwl (32) t awd (39) t cwd (38) t oed (53) t oea (52) t dh (34) t clz (12) t aa (15) col address data out data in data in data out ras cas address we i/o oe i/o i/o we oe we oe read cycle write cycle read-write cycle t oea (52) t roh (53) t csr (48) t rcs (17) t ds (33) t oez (54)
a426316b series prelimina ry ( november , 2000, version 0.0) 19 amic technology, inc. hidden refresh cycle (word read) t ras(3) t rp(2 ) t rc(1) t crp(9) t ar(16) t rcd(5) t asr(10) t crp(9) t asc(24) t cah(25) t rad(6) a0 ~ a7 ucas lcas ras t rah(11) t rrh(19) t rcs(17) i/o 0 ~ i/o 15 : high or low oe high-z t ras(3) t rp(2 ) t chr(49) t rc(1) t rsh(7) t ral(20) t cac(14) t off(23) t aa(15) t clz(12) t rac(13) we row column valid data-out
a426316b series prelimina ry ( november , 2000, version 0.0) 20 amic technology, inc. hidden refresh cycle (early word write) t ras(3) t rp(2 ) t rc(1) t crp(9) t ar(16) t rcd(5) t asr(10) t crp(9) t asc(24) t cah(25) t rad(6) a0 ~ a7 ras t rah(11) : high or low oe t ras(3) t rp(2 ) t chr(49) t rc(1) t rsh(7) t ral(20) we row column t wcs(27) t wch(28) t wp(30) t ds(33) t dh(34) valid data-in i/o 0 ~ i/o 15 ucas lcas
a426316b series prelimina ry ( november , 2000, version 0.0) 21 amic technology, inc. self refresh mode (a426316b - l only) n self refr esh mode. a. entering the self refresh mode: the a426316b - l self refresh mode is entered by using cas before ras cycle and holding ras and cas signal ?low? longer than 300 m s. b. cont inuing the self refresh mode: the self refresh mode is continued by holding ras ?low? after entering the self refresh mode. it does not depend on cas being ?high? or ?low? after entering the self refresh mode continu e the self refresh mode. c. exiting the self refresh mode: the a426316b exits the self refresh mode when the ras signal is brought ?high?. t rass(40) t pr(2) t crp(9) t csr(48) t rpc(50) ras t rps(26) t chs(21) t asr(10) t cpn(41) t off(23) a0 ~ a7 : high or low high-z i/o 0 ~ i/o 15 ucas lcas row col note: we, oe = don't care.
a426316b series prelimina ry ( november , 2000, version 0.0) 22 amic technology, inc. capacitance 15 (f = 1mhz, ta = room temperature, vcc = 5v 10%) symbol signals parameter max. u nit test conditions c in1 a0 ? a7 5 pf vin = 0v c in2 ras , ucas , lcas , we , oe input capacitance 7 pf vin = 0v c i/o i/o 0 - i/o 15 i/o capacitance 7 pf vin = v out = 0v ordering codes package \ ras access time 30ns 35ns 40ns self - refresh 40l soj (400 mil) a426316bs - 30 a426316bs - 35 a426316bs - 40 no 40/44l tsop type ii (400mil) a426316bv - 30 a426316bv - 35 a426316bv - 40 no 40l soj (400mil) a42631 6bs - 30l a426316bs - 35l a426316bs - 40l yes 40/44l tsop ii (400mil) a426316bv - 30l a426316bv - 35l a426316bv - 40l yes
a426316b series prelimina ry ( november , 2000, version 0.0) 23 amic technology, inc. package information soj 40l outline dimensions unit: inches/mm dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.144 - - 3.66 a 1 0.025 - - 0.64 - - a 2 0.105 0.110 0.115 2.67 2.79 2.92 b 1 0.026 0.028 0.032 0.66 0.71 0.81 b 0.016 0.018 0.022 0.41 0.46 0.56 c 0.008 0.010 0.014 0.20 0.25 0.36 d 1.020 1.025 1.030 25.91 26.04 26.16 e 0.395 0.400 0.405 10.03 10 .16 10.29 e 0.044 0.050 0.056 1.12 1.27 1.42 e 1 0.355 0.366 0.376 9.114 9.383 9.652 h e 0.430 0.440 0.450 10.92 11.18 11.43 l 0.081 0.093 0.105 2.083 2.39 2.70 s - - 0.050 - - 1.27 y - - 0.004 - - 0.10 q 0 - 10 0 - 10 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e does not include resin fins. 3. dimension e 1 is for pc board surface mount pad pitch design reference only. 4. dimension s includes end flash. 1 e h e 20 21 40 a 1 a 2 e e 1 c s d seating plane d y l 1 a b b q
a426316b series prelimina ry ( november , 2000, version 0.0) 24 amic technology, inc. package info rmation tsop 40/44l (type ii) outline dimensions unit: inches/mm 1 e h e l 1 l 1 c 44 a 1 a 2 a s d y e d b l l q dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.047 - - 1.20 a 1 0.002 - 0.006 0.05 - 0.15 a 2 0.037 0.039 0.041 0.95 1.00 1.05 b 0.013 0.015 0.017 0.32 0.37 0.42 c 0.003 0.005 0.009 0.08 0.13 0.23 d 0.720 0.725 0.730 18.28 18.41 18.54 e 0.395 0.400 0.405 10.03 10.16 10.29 e 0.031 bsc 0.80 bsc h e 0.455 0.463 0.471 11.56 11.76 11.96 l 0.016 0.020 0.024 0.40 0.50 0.60 l 1 - 0. 031 - - 0.80 - s - - 0.035 - - 0.90 y - - 0.004 - - 0.10 q 1 3 5 1 3 5 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e does not include resin fins. 3. dimension s includes end flash.

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